http://27.109.7.66:8080/xmlui/handle/123456789/2631 Sun, 05 Apr 2026 01:14:37 GMT 2026-04-05T01:14:37Z http://27.109.7.66:8080/xmlui/handle/123456789/3571 Digital logic design (2025) SET School of Engineering and Technology, Navrachana University Mon, 19 May 2025 00:00:00 GMT http://27.109.7.66:8080/xmlui/handle/123456789/3571 2025-05-19T00:00:00Z http://27.109.7.66:8080/xmlui/handle/123456789/3073 Digital logic design (2024) SET School of Engineering and Technology, Navrachana University Tue, 14 May 2024 00:00:00 GMT http://27.109.7.66:8080/xmlui/handle/123456789/3073 2024-05-14T00:00:00Z http://27.109.7.66:8080/xmlui/handle/123456789/2632 Digital logic design (2023) SET (School of Engineering and Technology, Navrachana University) SET (School of Engineering and Technology) 2nd End Semester Examination, 15-04-2023 Sat, 15 Apr 2023 00:00:00 GMT http://27.109.7.66:8080/xmlui/handle/123456789/2632 2023-04-15T00:00:00Z